| Opcode/Instruction | Op /En | 64/32 bit Mode Support | CPUID Feature Flag | Description |
|---|---|---|---|---|
|
EVEX.NDS.LIG.66.0F38.W1 CB /r VRCP28SD xmm1 {k1}{z}, xmm2, xmm3/m64 {sae} |
T1S | V/V | AVX512ER | Computes the approximate reciprocal ( < 2^-28 relative error) of the scalar double-precision floating-point value in xmm3/m64 and stores the results in xmm1. Under writemask. Also, upper double-precision floating-point value (bits[127:64]) from xmm2 is copied to xmm1[127:64]. |
| Op/En | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
| T1S | ModRM:reg (w) | EVEX.vvvv | ModRM:r/m (r) | NA |
Description
Computes the reciprocal approximation of the low float64 value in the second source operand (the third operand) and store the result to the destination operand (the first operand). The approximate reciprocal is evaluated with less than 2^-28 of maximum relative error. The result is written into the low float64 element of the destination operand according to the writemask k1. Bits 127:64 of the destination is copied from the corresponding bits of the first source operand (the second operand).
A denormal input value is treated as zero and does not signal #DE, irrespective of MXCSR.DAZ. A denormal result is flushed to zero and does not signal #UE, irrespective of MXCSR.FZ.
If any source element is NaN, the quietized NaN source value is returned for that element. If any source element is ±∞, ±0.0 is returned for that element. Also, if any source element is ±0.0, ±∞ is returned for that element.
The first source operand is an XMM register. The second source operand is an XMM register or a 64-bit memory location. The destination operand is a XMM register, conditionally updated using writemask k1.
A numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/refer-ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.
Operation
VRCP28SD ((EVEX encoded versions)
IF k1[0] OR *no writemask* THEN
DEST[63: 0] (cid:197) RCP_28_DP(1.0/SRC2[63: 0]);
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63: 0] remains unchanged*
ELSE
; zeroing-masking
DEST[63: 0] (cid:197) 0
FI;
FI;
ENDFOR;
DEST[127:64] (cid:197) SRC1[127: 64]
DEST[MAX_VL-1:128] (cid:197) 0
| Input value | Result value | Comments |
|---|---|---|
| NAN | QNAN(input) | If (SRC = SNaN) then #I |
| 0 ≤ X < 2-1022 | INF | Positive input denormal or zero; #Z |
| -2-1022 < X ≤ -0 | -INF | Negative input denormal or zero; #Z |
| X > 21022 | +0.0f | |
| X < -21022 | -0.0f | |
| X = +∞ | +0.0f | |
| X = -∞ | -0.0f | |
| X = 2-n | 2n | Exact result (unless input/output is a denormal) |
| X = -2-n | -2n | Exact result (unless input/output is a denormal) |
Intel C/C++ Compiler Intrinsic Equivalent
VRCP28SD __m128d _mm_rcp28_round_sd ( __m128d a, __m128d b, int sae);
VRCP28SD __m128d _mm_mask_rcp28_round_sd(__m128d s, __mmask8 m, __m128d a, __m128d b, int sae);
VRCP28SD __m128d _mm_maskz_rcp28_round_sd(__mmask8 m, __m128d a, __m128d b, int sae);
SIMD Floating-Point Exceptions
Invalid (if SNaN input), Divide-by-zero
Other Exceptions
See Exceptions Type E3.