VGETMANTPS—Extract Float32 Vector of Normalized Mantissas from Float32 Vector

Instruction Operand Encoding

Description

Convert single-precision floating values in the source operand (the second operand) to SP FP values with the mantissa normalization and sign control specified by the imm8 byte, see Figure 5-15. The converted results are written to the destination operand (the first operand) using writemask k1. The normalized mantissa is specified by interv (imm8[1:0]) and the sign control (sc) is specified by bits 3:2 of the immediate byte.

The destination operand is a ZMM/YMM/XMM register updated under the writemask. The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-bit memory location.

For each input SP FP value x, The conversion operation is:

GetMant(x) = ±2^k|x.significand|

where:

1 <= |x.significand| < 2

Unbiased exponent k depends on the interval range defined by interv and whether the exponent of the source is even or odd. The sign of the final result is determined by sc and the source sign.

if interv != 0 then k = -1, otherwise K = 0. The encoded value of imm8[1:0] and sign control are shown in Figure 5-15.

Each converted SP FP result is encoded according to the sign control, the unbiased exponent k (adding bias) and a mantissa normalized to the range specified by interv.

The GetMant() function follows Table 5-9 when dealing with floating-point special numbers.

This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1 are computed and stored into the destination. Elements in zmm1 with the corresponding bit clear in k1 retain their previous values.

Note: EVEX.vvvv is reserved and must be 1111b, VEX.L must be 0; otherwise instructions will #UD.

Operation

GetNormalizeMantissaSP(SRC[31:0] , SignCtrl[1:0], Interv[1:0])

{

// Extracting the SRC sign, exponent and mantissa fields

Dst.sign (cid:197) SignCtrl[0] ? 0 : Src[31];

// Get sign bit

Dst.exp (cid:197) SRC[30:23];

; Get original exponent value

Dst.fraction (cid:197) SRC[22:0];; Get original fraction value

ZeroOperand (cid:197) (Dst.exp = 0) AND (Dst.fraction = 0);

DenormOperand (cid:197) (Dst.exp = 0h) AND (Dst.fraction != 0);

InfiniteOperand (cid:197) (Dst.exp = 0FFh) AND (Dst.fraction = 0);

NaNOperand (cid:197) (Dst.exp = 0FFh) AND (Dst.fraction != 0);

// Check for NAN operand

IF (NaNOperand)

{

IF (SRC = SNaN) {Set #IE;}

Return QNAN(SRC);

}

// Check for Zero and Infinite operands

IF ((ZeroOperand) OR (InfiniteOperand)

{

Dst.exp (cid:197) 07Fh;

// Override exponent with BIAS

Return ((Dst.sign<<31) | (Dst.exp<<23) | (Dst.fraction));

}

// Check for negative operand (including -0.0)

IF ((Src[31] = 1) AND SignCtrl[1])

{

Set #IE;

Return QNaN_Indefinite;

}

// Checking for denormal operands

IF (DenormOperand)

{

IF (MXCSR.DAZ=1) Dst.fraction (cid:197) 0;// Zero out fraction

ELSE

{

// Jbit is the hidden integral bit. Zero in case of denormal operand.

Src.Jbit (cid:197) 0;

// Zero Src Jbit

Dst.exp (cid:197) 07Fh;

// Override exponent with BIAS

WHILE (Src.Jbit = 0) {

// normalize mantissa

Src.Jbit (cid:197) Dst.fraction[22];

// Get the fraction MSB

Dst.fraction (cid:197) (Dst.fraction << 1);

// Start normalizing the mantissa

Dst.exp-- ;

// Adjust the exponent

}

SET #DE;

// Set DE bit

}

}

// At this point, Dst.fraction is normalized.

// Checking for exponent response

Unbiased.exp (cid:197) Dst.exp – 07Fh;

// subtract the bias from exponent

IsOddExp (cid:197) Unbiased.exp[0];

// recognized unbiased ODD exponent

SignalingBit (cid:197) Dst.fraction[22];

CASE (interv[1:0])

00: Dst.exp (cid:197) 07Fh;

// This is the bias

01: Dst.exp (cid:197) (IsOddExp) ? 07Eh : 07Fh;

// either bias-1, or bias

10: Dst.exp (cid:197) 07Eh;

// bias-1

11: Dst.exp (cid:197) (SignalingBit) ? 07Eh : 07Fh;

// either bias-1, or bias

ESCA

// Form the final destination

DEST[31:0] (cid:197) (Dst.sign << 31) OR (Dst.exp << 23) OR (Dst.fraction);

Return (DEST);

}

SignCtrl[1:0] (cid:197) IMM8[3:2];

Interv[1:0] (cid:197) IMM8[1:0];

VGETMANTPS (EVEX encoded versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j (cid:197) 0 TO KL-1

i (cid:197) j * 32

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1) AND (SRC *is memory*)

THEN

DEST[i+31:i] (cid:197)(cid:3)GetNormalizedMantissaSP(SRC[31:0], sc, interv)

ELSE

DEST[i+31:i] (cid:197)(cid:3)GetNormalizedMantissaSP(SRC[i+31:i], sc, interv)

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] (cid:197) 0

FI

FI;

ENDFOR

DEST[MAX_VL-1:VL] (cid:197) 0

Intel C/C++ Compiler Intrinsic Equivalent

VGETMANTPS __m512 _mm512_getmant_ps( __m512 a, enum intv, enum sgn);

VGETMANTPS __m512 _mm512_mask_getmant_ps(__m512 s, __mmask16 k, __m512 a, enum intv, enum sgn;

VGETMANTPS __m512 _mm512_maskz_getmant_ps(__mmask16 k, __m512 a, enum intv, enum sgn);

VGETMANTPS __m512 _mm512_getmant_round_ps( __m512 a, enum intv, enum sgn, int r);

VGETMANTPS __m512 _mm512_mask_getmant_round_ps(__m512 s, __mmask16 k, __m512 a, enum intv, enum sgn, int r);

VGETMANTPS __m512 _mm512_maskz_getmant_round_ps(__mmask16 k, __m512 a, enum intv, enum sgn, int r);

VGETMANTPS __m256 _mm256_getmant_ps( __m256 a, enum intv, enum sgn);

VGETMANTPS __m256 _mm256_mask_getmant_ps(__m256 s, __mmask8 k, __m256 a, enum intv, enum sgn);

VGETMANTPS __m256 _mm256_maskz_getmant_ps( __mmask8 k, __m256 a, enum intv, enum sgn);

VGETMANTPS __m128 _mm_getmant_ps( __m128 a, enum intv, enum sgn);

VGETMANTPS __m128 _mm_mask_getmant_ps(__m128 s, __mmask8 k, __m128 a, enum intv, enum sgn);

VGETMANTPS __m128 _mm_maskz_getmant_ps( __mmask8 k, __m128 a, enum intv, enum sgn);

SIMD Floating-Point Exceptions

Denormal, Invalid

Other Exceptions

See Exceptions Type E2.