| Opcode/Instruction | Op /En | 64/32 bit Mode Support | CPUID Feature Flag | Description |
|---|---|---|---|---|
|
EVEX.LIG.66.0F3A.W0 67 /r VFPCLASSSS k2 {k1}, xmm2/m32, imm8 |
T1S | V/V | AVX512DQ | Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result. |
| Op/En | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
| T1S | ModRM:reg (w) | ModRM:r/m (r) | NA | NA |
Description
The FPCLASSSS instruction checks the low single-precision floating point value in the source operand for special categories, specified by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the input data element is classified against. The classified results of all specified categories of an input value are ORed together to form the final boolean result for the input element. The result is written to the low bit in a mask register k2 according to the writemask k1. Bits MAX_KL-1: 1 of the destination are cleared.
The classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category is listed in Table 5-6.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
CheckFPClassSP (tsrc[31:0], imm8[7:0]){
//* Start checking the source operand for special type *//
NegNum (cid:197) tsrc[31];
IF (tsrc[30:23]=0FFh) Then ExpAllOnes (cid:197) 1; FI;
IF (tsrc[30:23]=0h) Then ExpAllZeros (cid:197) 1;
IF (ExpAllZeros AND MXCSR.DAZ) Then
MantAllZeros (cid:197) 1;
ELSIF (tsrc[22:0]=0h) Then
MantAllZeros (cid:197) 1;
FI;
ZeroNumber= ExpAllZeros AND MantAllZeros
SignalingBit= tsrc[22];
sNaN_res (cid:197) ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit) ; // sNaN
qNaN_res (cid:197) ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit;; // qNaN
Pzero_res (cid:197) NOT(NegNum) AND ExpAllZeros AND MantAllZeros;; // +0
Nzero_res (cid:197) NegNum AND ExpAllZeros AND MantAllZeros;; // -0
PInf_res (cid:197) NOT(NegNum) AND ExpAllOnes AND MantAllZeros;; // +Inf
NInf_res (cid:197) NegNum AND ExpAllOnes AND MantAllZeros;; // -Inf
Denorm_res (cid:197) ExpAllZeros AND NOT(MantAllZeros);; // denorm
FinNeg_res (cid:197) NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber);; // -finite
bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR
( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR
( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR
( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res ) ;
Return bResult;
} //* end of CheckSPClassSP() *//
VFPCLASSSS (EVEX encoded version)
IF k1[0] OR *no writemask*
THEN DEST[0] (cid:197)
CheckFPClassSP(SRC1[31:0], imm8[7:0])
ELSE DEST[0] (cid:197) 0
; zeroing-masking only
FI; DEST[MAX_KL-1:1] (cid:197) 0
Intel C/C++ Compiler Intrinsic Equivalent
VFPCLASSSS __mmask8 _mm_fpclass_ss_mask( __m128 a, int c)
VFPCLASSSS __mmask8 _mm_mask_fpclass_ss_mask( __mmask8 m, __m128 a, int c)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type E6
| #UD | If EVEX.vvvv != 1111B. |