VFPCLASSPD—Tests Types Of a Packed Float64 Values

Opcode/Instruction	Op /En	64/32 bit Mode Support	CPUID Feature Flag	Description
EVEX.128.66.0F3A.W1 66 /r ib VFPCLASSPD k2 {k1}, xmm2/m128/m64bcst, imm8	FV	V/V	AVX512VL AVX512DQ	NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.
EVEX.256.66.0F3A.W1 66 /r ib VFPCLASSPD k2 {k1}, ymm2/m256/m64bcst, imm8	FV	V/V	AVX512VL AVX512DQ	NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.
EVEX.512.66.0F3A.W1 66 /r ib VFPCLASSPD k2 {k1}, zmm2/m512/m64bcst, imm8	FV	V/V	AVX512DQ	NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.

Opcode/Instruction

Op /En

64/32 bit Mode Support

CPUID Feature Flag

Description

EVEX.128.66.0F3A.W1 66 /r ib

VFPCLASSPD k2 {k1}, xmm2/m128/m64bcst, imm8

V/V

AVX512VL

AVX512DQ

NaN, +0, -0,

+Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.

EVEX.256.66.0F3A.W1 66 /r ib

VFPCLASSPD k2 {k1}, ymm2/m256/m64bcst, imm8

V/V

AVX512VL

AVX512DQ

NaN, +0, -0,

+Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.

EVEX.512.66.0F3A.W1 66 /r ib

VFPCLASSPD k2 {k1}, zmm2/m512/m64bcst, imm8

V/V

AVX512DQ

NaN, +0, -0,

+Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.

Instruction Operand Encoding

Op/En	Operand 1	Operand 2	Operand 3	Operand 4
FV	ModRM:reg (w)	ModRM:r/m (r)	NA	NA

Description

The FPCLASSPD instruction checks the packed double precision floating point values for special categories, speci-fied by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the input data element is classified against. The classified results of all specified categories of an input value are ORed together to form the final boolean result for the input element. The result of each element is written to the corre-sponding bit in a mask register k2 according to the writemask k1. Bits [MAX_KL-1:8/4/2] of the destination are cleared.

The classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category is listed in Table 5-6.

SNaN

Neg. Finite

Denormal

Neg. INF

+INF

Neg. 0

QNaN

Figure 5-13. Imm8 Byte Specifier of Special Case FP Values for VFPCLASSPD/SD/PS/SS

Table 5-6. Classifier Operations for VFPCLASSPD/SD/PS/SS

Bits	Imm8[0]	Imm8[1]	Imm8[2]	Imm8[3]	Imm8[4]	Imm8[5]	Imm8[6]	Imm8[7]
Category	QNAN	PosZero	NegZero	PosINF	NegINF	Denormal	Negative	SNAN
Classifier	Checks for QNaN	Checks for +0	Checks for -0	Checks for +INF	Checks for -INF	Checks for Denormal	Checks for Negative finite	Checks for SNaN

The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation

CheckFPClassDP (tsrc[63:0], imm8[7:0]){

//* Start checking the source operand for special type *//

NegNum (cid:197) tsrc[63];

IF (tsrc[62:52]=07FFh) Then ExpAllOnes (cid:197) 1; FI;

IF (tsrc[62:52]=0h) Then ExpAllZeros (cid:197) 1;

IF (ExpAllZeros AND MXCSR.DAZ) Then

MantAllZeros (cid:197) 1;

ELSIF (tsrc[51:0]=0h) Then

MantAllZeros (cid:197) 1;

FI;

ZeroNumber (cid:197) ExpAllZeros AND MantAllZeros

SignalingBit (cid:197) tsrc[51];

sNaN_res (cid:197) ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit) ; // sNaN

qNaN_res (cid:197) ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit;; // qNaN

Pzero_res (cid:197) NOT(NegNum) AND ExpAllZeros AND MantAllZeros;; // +0

Nzero_res (cid:197) NegNum AND ExpAllZeros AND MantAllZeros;; // -0

PInf_res (cid:197) NOT(NegNum) AND ExpAllOnes AND MantAllZeros;; // +Inf

NInf_res (cid:197) NegNum AND ExpAllOnes AND MantAllZeros;; // -Inf

Denorm_res (cid:197) ExpAllZeros AND NOT(MantAllZeros);; // denorm

FinNeg_res (cid:197) NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber);; // -finite

bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR

( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR

( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR

( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res ) ;

Return bResult;

} //* end of CheckFPClassDP() *//

VFPCLASSPD (EVEX Encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j (cid:197) 0 TO KL-1

i (cid:197) j * 64

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b == 1) AND (SRC *is memory*)

THEN

DEST[j] (cid:197) CheckFPClassDP(SRC1[63:0], imm8[7:0]);

ELSE

DEST[j] (cid:197) CheckFPClassDP(SRC1[i+63:i], imm8[7:0]);

FI;

ELSE DEST[j] (cid:197) 0

; zeroing-masking only

FI;

ENDFOR

DEST[MAX_KL-1:KL] (cid:197) 0

Intel C/C++ Compiler Intrinsic Equivalent

VFPCLASSPD __mmask8 _mm512_fpclass_pd_mask( __m512d a, int c);

VFPCLASSPD __mmask8 _mm512_mask_fpclass_pd_mask( __mmask8 m, __m512d a, int c)

VFPCLASSPD __mmask8 _mm256_fpclass_pd_mask( __m256d a, int c)

VFPCLASSPD __mmask8 _mm256_mask_fpclass_pd_mask( __mmask8 m, __m256d a, int c)

VFPCLASSPD __mmask8 _mm_fpclass_pd_mask( __m128d a, int c)

VFPCLASSPD __mmask8 _mm_mask_fpclass_pd_mask( __mmask8 m, __m128d a, int c)

SIMD Floating-Point Exceptions

None

Other Exceptions

See Exceptions Type E4

#UD	If EVEX.vvvv != 1111B.