VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD—Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values

Opcode/Instruction Op/En 64/32 bit Mode Support CPUID Feature Flag Description

VEX.NDS.128.66.0F38.W1 9E /r

VFNMSUB132PD xmm1, xmm2, xmm3/m128

 RVM V/V FMA Multiply packed double-precision floating-point values from xmm1 and xmm3/mem, negate the multiplication result and subtract xmm2 and put result in xmm1.

VEX.NDS.128.66.0F38.W1 AE /r

VFNMSUB213PD xmm1, xmm2, xmm3/m128

 RVM V/V FMA Multiply packed double-precision floating-point values from xmm1 and xmm2, negate the multiplication result and subtract xmm3/mem and put result in xmm1.

VEX.NDS.128.66.0F38.W1 BE /r

VFNMSUB231PD xmm1, xmm2, xmm3/m128

 RVM V/V FMA Multiply packed double-precision floating-point values from xmm2 and xmm3/mem, negate the multiplication result and subtract xmm1 and put result in xmm1.

VEX.NDS.256.66.0F38.W1 9E /r

VFNMSUB132PD ymm1, ymm2, ymm3/m256

 RVM V/V FMA Multiply packed double-precision floating-point values from ymm1 and ymm3/mem, negate the multiplication result and subtract ymm2 and put result in ymm1.

VEX.NDS.256.66.0F38.W1 AE /r

VFNMSUB213PD ymm1, ymm2, ymm3/m256

 RVM V/V FMA Multiply packed double-precision floating-point values from ymm1 and ymm2, negate the multiplication result and subtract ymm3/mem and put result in ymm1.

VEX.NDS.256.66.0F38.W1 BE /r

VFNMSUB231PD ymm1, ymm2, ymm3/m256

 RVM V/V FMA Multiply packed double-precision floating-point values from ymm2 and ymm3/mem, negate the multiplication result and subtract ymm1 and put result in ymm1.

EVEX.NDS.128.66.0F38.W1 9E /r

VFNMSUB132PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst

 FV V/V

AVX512VL

AVX512F

 Multiply packed double-precision floating-point values from xmm1 and xmm3/m128/m64bcst, negate the multiplication result and subtract xmm2 and put result in xmm1.

EVEX.NDS.128.66.0F38.W1 AE /r

VFNMSUB213PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst

 FV V/V

AVX512VL

AVX512F

 Multiply packed double-precision floating-point values from xmm1 and xmm2, negate the multiplication result and subtract xmm3/m128/m64bcst and put result in xmm1.

EVEX.NDS.128.66.0F38.W1 BE /r

VFNMSUB231PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst

 FV V/V

AVX512VL

AVX512F

 Multiply packed double-precision floating-point values from xmm2 and xmm3/m128/m64bcst, negate the multiplication result and subtract xmm1 and put result in xmm1.

EVEX.NDS.256.66.0F38.W1 9E /r

VFNMSUB132PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst

 FV V/V

AVX512VL

AVX512F

 Multiply packed double-precision floating-point values from ymm1 and ymm3/m256/m64bcst, negate the multiplication result and subtract ymm2 and put result in ymm1.

EVEX.NDS.256.66.0F38.W1 AE /r

VFNMSUB213PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst

 FV V/V

AVX512VL

AVX512F

 Multiply packed double-precision floating-point values from ymm1 and ymm2, negate the multiplication result and subtract ymm3/m256/m64bcst and put result in ymm1.

EVEX.NDS.256.66.0F38.W1 BE /r

VFNMSUB231PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst

 FV V/V

AVX512VL

AVX512F

 Multiply packed double-precision floating-point values from ymm2 and ymm3/m256/m64bcst, negate the multiplication result and subtract ymm1 and put result in ymm1.

EVEX.NDS.512.66.0F38.W1 9E /r

VFNMSUB132PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}

 FV V/V AVX512F Multiply packed double-precision floating-point values from zmm1 and zmm3/m512/m64bcst, negate the multiplication result and subtract zmm2 and put result in zmm1.

EVEX.NDS.512.66.0F38.W1 AE /r

VFNMSUB213PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}

 FV V/V AVX512F Multiply packed double-precision floating-point values from zmm1 and zmm2, negate the multiplication result and subtract zmm3/m512/m64bcst and put result in zmm1.

EVEX.NDS.512.66.0F38.W1 BE /r

VFNMSUB231PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}

 FV V/V AVX512F Multiply packed double-precision floating-point values from zmm2 and zmm3/m512/m64bcst, negate the multiplication result and subtract zmm1 and put result in zmm1.

Instruction Operand Encoding

Op/En Operand 1 Operand 2 Operand 3 Operand 4
RVM ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA
FV ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) NA

Description

VFNMSUB132PD: Multiplies the two, four or eight packed double-precision floating-point values from the first source operand to the two, four or eight packed double-precision floating-point values in the third source operand. From negated infinite precision intermediate results, subtracts the two, four or eight packed double-precision floating-point values in the second source operand, performs rounding and stores the resulting two, four or eight packed double-precision floating-point values to the destination operand (first source operand).

VFNMSUB213PD: Multiplies the two, four or eight packed double-precision floating-point values from the second source operand to the two, four or eight packed double-precision floating-point values in the first source operand. From negated infinite precision intermediate results, subtracts the two, four or eight packed double-precision floating-point values in the third source operand, performs rounding and stores the resulting two, four or eight packed double-precision floating-point values to the destination operand (first source operand).

VFNMSUB231PD: Multiplies the two, four or eight packed double-precision floating-point values from the second source to the two, four or eight packed double-precision floating-point values in the third source operand. From negated infinite precision intermediate results, subtracts the two, four or eight packed double-precision floating-point values in the first source operand, performs rounding and stores the resulting two, four or eight packed double-precision floating-point values to the destination operand (first source operand).

EVEX encoded versions: The destination operand (also first source operand) and the second source operand are ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-tion or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is condition-ally updated with write mask k1.

VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a YMM register or a 256-bit memory location and encoded in rm_field.

VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination register are zeroed.

Operation

In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no rounding).

VFNMSUB132PD DEST, SRC2, SRC3 (VEX encoded version)

IF (VEX.128) THEN

MAXNUM (cid:197)2

ELSEIF (VEX.256)

MAXNUM (cid:197) 4

FI

For i = 0 to MAXNUM-1 {

n (cid:197) 64*i;

DEST[n+63:n] (cid:197) RoundFPControl_MXCSR( - (DEST[n+63:n]*SRC3[n+63:n]) - SRC2[n+63:n])

}

IF (VEX.128) THEN

DEST[MAX_VL-1:128] (cid:197) 0

ELSEIF (VEX.256)

DEST[MAX_VL-1:256] (cid:197) 0

FI

VFNMSUB213PD DEST, SRC2, SRC3 (VEX encoded version)

IF (VEX.128) THEN

MAXNUM (cid:197)2

ELSEIF (VEX.256)

MAXNUM (cid:197) 4

FI

For i = 0 to MAXNUM-1 {

n (cid:197) 64*i;

DEST[n+63:n] (cid:197) RoundFPControl_MXCSR( - (SRC2[n+63:n]*DEST[n+63:n]) - SRC3[n+63:n])

}

IF (VEX.128) THEN

DEST[MAX_VL-1:128] (cid:197) 0

ELSEIF (VEX.256)

DEST[MAX_VL-1:256] (cid:197) 0

FI

VFNMSUB231PD DEST, SRC2, SRC3 (VEX encoded version)

IF (VEX.128) THEN

MAXNUM (cid:197)2

ELSEIF (VEX.256)

MAXNUM (cid:197) 4

FI

For i = 0 to MAXNUM-1 {

n (cid:197) 64*i;

DEST[n+63:n] (cid:197) RoundFPControl_MXCSR( - (SRC2[n+63:n]*SRC3[n+63:n]) - DEST[n+63:n])

}

IF (VEX.128) THEN

DEST[MAX_VL-1:128] (cid:197) 0

ELSEIF (VEX.256)

DEST[MAX_VL-1:256] (cid:197) 0

FI

VFNMSUB132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

(KL, VL) = (2, 128), (4, 256), (8, 512)

IF (VL = 512) AND (EVEX.b = 1)

THEN

SET_RM(EVEX.RC);

ELSE

SET_RM(MXCSR.RM);

FI;

FOR j (cid:197) 0 TO KL-1

i (cid:197) j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] (cid:197)

RoundFPControl(-(DEST[i+63:i]*SRC3[i+63:i]) - SRC2[i+63:i])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] (cid:197) 0

FI

FI;

ENDFOR

DEST[MAX_VL-1:VL] (cid:197) 0

VFNMSUB132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j (cid:197) 0 TO KL-1

i (cid:197) j * 64

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1)

THEN

DEST[i+63:i] (cid:197)

RoundFPControl_MXCSR(-(DEST[i+63:i]*SRC3[63:0]) - SRC2[i+63:i])

ELSE

DEST[i+63:i] (cid:197)

RoundFPControl_MXCSR(-(DEST[i+63:i]*SRC3[i+63:i]) - SRC2[i+63:i])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] (cid:197) 0

FI

FI;

ENDFOR

DEST[MAX_VL-1:VL] (cid:197) 0

VFNMSUB213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

(KL, VL) = (2, 128), (4, 256), (8, 512)

IF (VL = 512) AND (EVEX.b = 1)

THEN

SET_RM(EVEX.RC);

ELSE

SET_RM(MXCSR.RM);

FI;

FOR j (cid:197) 0 TO KL-1

i (cid:197) j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] (cid:197)

RoundFPControl(-(SRC2[i+63:i]*DEST[i+63:i]) - SRC3[i+63:i])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] (cid:197) 0

FI

FI;

ENDFOR

DEST[MAX_VL-1:VL] (cid:197) 0

VFNMSUB213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j (cid:197) 0 TO KL-1

i (cid:197) j * 64

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1)

THEN

DEST[i+63:i] (cid:197)

RoundFPControl_MXCSR(-(SRC2[i+63:i]*DEST[i+63:i]) - SRC3[63:0])

ELSE

DEST[i+63:i] (cid:197)

RoundFPControl_MXCSR(-(SRC2[i+63:i]*DEST[i+63:i]) - SRC3[i+63:i])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] (cid:197) 0

FI

FI;

ENDFOR

DEST[MAX_VL-1:VL] (cid:197) 0

VFNMSUB231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

(KL, VL) = (2, 128), (4, 256), (8, 512)

IF (VL = 512) AND (EVEX.b = 1)

THEN

SET_RM(EVEX.RC);

ELSE

SET_RM(MXCSR.RM);

FI;

FOR j (cid:197) 0 TO KL-1

i (cid:197) j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] (cid:197)

RoundFPControl(-(SRC2[i+63:i]*SRC3[i+63:i]) - DEST[i+63:i])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] (cid:197) 0

FI

FI;

ENDFOR

DEST[MAX_VL-1:VL] (cid:197) 0

VFNMSUB231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j (cid:197) 0 TO KL-1

i (cid:197) j * 64

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1)

THEN

DEST[i+63:i] (cid:197)

RoundFPControl_MXCSR(-(SRC2[i+63:i]*SRC3[63:0]) - DEST[i+63:i])

ELSE

DEST[i+63:i] (cid:197)

RoundFPControl_MXCSR(-(SRC2[i+63:i]*SRC3[i+63:i]) - DEST[i+63:i])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] (cid:197) 0

FI

FI;

ENDFOR

DEST[MAX_VL-1:VL] (cid:197) 0

Intel C/C++ Compiler Intrinsic Equivalent

VFNMSUBxxxPD __m512d _mm512_fnmsub_pd(__m512d a, __m512d b, __m512d c);

VFNMSUBxxxPD __m512d _mm512_fnmsub_round_pd(__m512d a, __m512d b, __m512d c, int r);

VFNMSUBxxxPD __m512d _mm512_mask_fnmsub_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);

VFNMSUBxxxPD __m512d _mm512_maskz_fnmsub_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);

VFNMSUBxxxPD __m512d _mm512_mask3_fnmsub_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);

VFNMSUBxxxPD __m512d _mm512_mask_fnmsub_round_pd(__m512d a, __mmask8 k, __m512d b, __m512d c, int r);

VFNMSUBxxxPD __m512d _mm512_maskz_fnmsub_round_pd(__mmask8 k, __m512d a, __m512d b, __m512d c, int r);

VFNMSUBxxxPD __m512d _mm512_mask3_fnmsub_round_pd(__m512d a, __m512d b, __m512d c, __mmask8 k, int r);

VFNMSUBxxxPD __m256d _mm256_mask_fnmsub_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);

VFNMSUBxxxPD __m256d _mm256_maskz_fnmsub_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);

VFNMSUBxxxPD __m256d _mm256_mask3_fnmsub_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);

VFNMSUBxxxPD __m128d _mm_mask_fnmsub_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);

VFNMSUBxxxPD __m128d _mm_maskz_fnmsub_pd(__mmask8 k, __m128d a, __m128d b, __m128d c);

VFNMSUBxxxPD __m128d _mm_mask3_fnmsub_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);

VFNMSUBxxxPD __m128d _mm_fnmsub_pd (__m128d a, __m128d b, __m128d c);

VFNMSUBxxxPD __m256d _mm256_fnmsub_pd (__m256d a, __m256d b, __m256d c);

SIMD Floating-Point Exceptions

Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions

VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.