VCVTTPD2QQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers

Opcode/Instruction Op /En 64/32 bit Mode Support CPUID Feature Flag Description

EVEX.128.66.0F.W1 7A /r

VCVTTPD2QQ xmm1 {k1}{z}, xmm2/m128/m64bcst

 FV V/V

AVX512VL

AVX512DQ

 Convert two packed double-precision floating-point values from zmm2/m128/m64bcst to two packed quadword integers in zmm1 using truncation with writemask k1.

EVEX.256.66.0F.W1 7A /r

VCVTTPD2QQ ymm1 {k1}{z}, ymm2/m256/m64bcst

 FV V/V

AVX512VL

AVX512DQ

 Convert four packed double-precision floating-point values from ymm2/m256/m64bcst to four packed quadword integers in ymm1 using truncation with writemask k1.

EVEX.512.66.0F.W1 7A /r

VCVTTPD2QQ zmm1 {k1}{z}, zmm2/m512/m64bcst{sae}

 FV V/V AVX512DQ Convert eight packed double-precision floating-point values from zmm2/m512 to eight packed quadword integers in zmm1 using truncation with writemask k1.

Instruction Operand Encoding

Op/En Operand 1 Operand 2 Operand 3 Operand 4
FV ModRM:reg (w) ModRM:r/m (r) NA NA

Description

Converts with truncation packed double-precision floating-point values in the source operand (second operand) to packed quadword integers in the destination operand (first operand).

EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (2w-1, where w represents the number of bits in the destination format) is returned.

Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation

VCVTTPD2QQ (EVEX encoded version) when src operand is a register

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j (cid:197) 0 TO KL-1

i (cid:197) j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] (cid:197)

Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[i+63:i])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] (cid:197) 0

FI

FI;

ENDFOR

DEST[MAX_VL-1:VL] (cid:197) 0

VCVTTPD2QQ (EVEX encoded version) when src operand is a memory source

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j (cid:197) 0 TO KL-1

i (cid:197) j * 64

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b == 1)

THEN

DEST[i+63:i] (cid:197)

Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[63:0])

ELSE

DEST[i+63:i] (cid:197) Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[i+63:i])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] (cid:197) 0

FI

FI;

ENDFOR

DEST[MAX_VL-1:VL] (cid:197) 0

Intel C/C++ Compiler Intrinsic Equivalent

VCVTTPD2QQ __m512i _mm512_cvttpd_epi64( __m512d a);

VCVTTPD2QQ __m512i _mm512_mask_cvttpd_epi64( __m512i s, __mmask8 k, __m512d a);

VCVTTPD2QQ __m512i _mm512_maskz_cvttpd_epi64( __mmask8 k, __m512d a);

VCVTTPD2QQ __m512i _mm512_cvtt_roundpd_epi64( __m512d a, int sae);

VCVTTPD2QQ __m512i _mm512_mask_cvtt_roundpd_epi64( __m512i s, __mmask8 k, __m512d a, int sae);

VCVTTPD2QQ __m512i _mm512_maskz_cvtt_roundpd_epi64( __mmask8 k, __m512d a, int sae);

VCVTTPD2QQ __m256i _mm256_mask_cvttpd_epi64( __m256i s, __mmask8 k, __m256d a);

VCVTTPD2QQ __m256i _mm256_maskz_cvttpd_epi64( __mmask8 k, __m256d a);

VCVTTPD2QQ __m128i _mm_mask_cvttpd_epi64( __m128i s, __mmask8 k, __m128d a);

VCVTTPD2QQ __m128i _mm_maskz_cvttpd_epi64( __mmask8 k, __m128d a);

SIMD Floating-Point Exceptions

Invalid, Precision

Other Exceptions

EVEX-encoded instructions, see Exceptions Type E2.
If EVEX.vvvv != 1111B.