SHA256MSG2—Perform a Final Calculation for the Next Four SHA256 Message Dwords

Opcode/Instruction	Op/En	64/32 bit Mode Support	CPUID Feature Flag	Description
0F 38 CD /r SHA256MSG2 xmm1, xmm2/m128	RM	V/V	SHA	Performs the final calculation for the next four SHA256 message dwords using previous message dwords from xmm1 and xmm2/m128, storing the result in xmm1.

Opcode/Instruction

Op/En

64/32 bit Mode Support

CPUID Feature Flag

Description

0F 38 CD /r

SHA256MSG2 xmm1, xmm2/m128

V/V

SHA

Performs the final calculation for the next four SHA256 message dwords using previous message dwords from xmm1 and xmm2/m128, storing the result in xmm1.

Instruction Operand Encoding

Op/En	Operand 1	Operand 2	Operand 3
RM	ModRM:reg (r, w)	ModRM:r/m (r)	NA

Description

The SHA256MSG2 instruction is one of two SHA2 message scheduling instructions. The instruction performs the final calculation for the next four SHA256 message dwords.

Operation

SHA256MSG2

W14 (cid:197) SRC2[95:64] ;

W15 (cid:197) SRC2[127:96] ;

W16 (cid:197) SRC1[31: 0] + σ₁( W14) ;

W17 (cid:197) SRC1[63: 32] + σ₁( W15) ;

W18 (cid:197) SRC1[95: 64] + σ₁( W16) ;

W19 (cid:197) SRC1[127: 96] + σ₁( W17) ;

DEST[127:96] (cid:197) W19 ;

DEST[95:64] (cid:197) W18 ;

DEST[63:32] (cid:197) W17 ;

DEST[31:0] (cid:197) W16;

Intel C/C++ Compiler Intrinsic Equivalent

SHA256MSG2 : __m128i _mm_sha256msg2_epu32(__m128i, __m128i);

Flags Affected

None

SIMD Floating-Point Exceptions

None

Other Exceptions

See Exceptions Type 4.