PSUBB/PSUBW/PSUBD—Subtract Packed Integers

Description CPUID Feature Flag Opcode/Instruction Op/En 64/32 bit Mode Support
Subtract packed byte integers in mm/m64 from packed byte integers in mm. MMX

0F F8 /r1

PSUBB mm, mm/m64

 RM V/V
Subtract packed byte integers in xmm2/m128 from packed byte integers in xmm1. SSE2

66 0F F8 /r

PSUBB xmm1, xmm2/m128

 RM V/V
Subtract packed word integers in mm/m64 from packed word integers in mm. MMX

0F F9 /r1

PSUBW mm, mm/m64

 RM V/V
Subtract packed word integers in xmm2/m128 from packed word integers in xmm1. SSE2

66 0F F9 /r

PSUBW xmm1, xmm2/m128

 RM V/V
Subtract packed doubleword integers in mm/m64 from packed doubleword integers in mm. MMX

0F FA /r1

PSUBD mm, mm/m64

 RM V/V
Subtract packed doubleword integers in xmm2/mem128 from packed doubleword integers in xmm1. SSE2

66 0F FA /r

PSUBD xmm1, xmm2/m128

 RM V/V
Subtract packed byte integers in xmm3/m128 from xmm2. AVX VEX.NDS.128.66.0F.WIG F8 /r VPSUBB xmm1, xmm2, xmm3/m128 RVM V/V
Subtract packed word integers in xmm3/m128 from xmm2. AVX

VEX.NDS.128.66.0F.WIG F9 /r

VPSUBW xmm1, xmm2, xmm3/m128

 RVM V/V
Subtract packed doubleword integers in xmm3/m128 from xmm2. AVX VEX.NDS.128.66.0F.WIG FA /r VPSUBD xmm1, xmm2, xmm3/m128 RVM V/V
Subtract packed byte integers in ymm3/m256 from ymm2. AVX2 VEX.NDS.256.66.0F.WIG F8 /r VPSUBB ymm1, ymm2, ymm3/m256 RVM V/V
Subtract packed word integers in ymm3/m256 from ymm2. AVX2 VEX.NDS.256.66.0F.WIG F9 /r VPSUBW ymm1, ymm2, ymm3/m256 RVM V/V
Subtract packed doubleword integers in ymm3/m256 from ymm2. AVX2 VEX.NDS.256.66.0F.WIG FA /r VPSUBD ymm1, ymm2, ymm3/m256 RVM V/V
Subtract packed byte integers in xmm3/m128 from xmm2 and store in xmm1 using writemask k1. AVX512VL AVX512BW

EVEX.NDS.128.66.0F.WIG F8 /r

VPSUBB xmm1 {k1}{z}, xmm2, xmm3/m128

 FVM V/V
Subtract packed byte integers in ymm3/m256 from ymm2 and store in ymm1 using writemask k1. AVX512VL AVX512BW

EVEX.NDS.256.66.0F.WIG F8 /r

VPSUBB ymm1 {k1}{z}, ymm2, ymm3/m256

 FVM V/V
Subtract packed byte integers in zmm3/m512 from zmm2 and store in zmm1 using writemask k1. AVX512BW

EVEX.NDS.512.66.0F.WIG F8 /r

VPSUBB zmm1 {k1}{z}, zmm2, zmm3/m512

 FVM V/V
Subtract packed word integers in xmm3/m128 from xmm2 and store in xmm1 using writemask k1. AVX512VL AVX512BW

EVEX.NDS.128.66.0F.WIG F9 /r

VPSUBW xmm1 {k1}{z}, xmm2, xmm3/m128

 FVM V/V
Subtract packed word integers in ymm3/m256 from ymm2 and store in ymm1 using writemask k1. AVX512VL AVX512BW

EVEX.NDS.256.66.0F.WIG F9 /r

VPSUBW ymm1 {k1}{z}, ymm2, ymm3/m256

 FVM V/V
Subtract packed word integers in zmm3/m512 from zmm2 and store in zmm1 using writemask k1. AVX512BW

EVEX.NDS.512.66.0F.WIG F9 /r

VPSUBW zmm1 {k1}{z}, zmm2, zmm3/m512

 FVM V/V

EVEX.NDS.128.66.0F.W0 FA /r

VPSUBD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst

 FV V/V AVX512VL AVX512F Subtract packed doubleword integers in xmm3/m128/m32bcst from xmm2 and store in xmm1 using writemask k1.

EVEX.NDS.256.66.0F.W0 FA /r

VPSUBD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst

 FV V/V AVX512VL AVX512F Subtract packed doubleword integers in ymm3/m256/m32bcst from ymm2 and store in ymm1 using writemask k1.

EVEX.NDS.512.66.0F.W0 FA /r

VPSUBD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst

 FV V/V AVX512F Subtract packed doubleword integers in zmm3/m512/m32bcst from zmm2 and store in zmm1 using writemask k1

NOTES:

1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En Operand 1 Operand 2 Operand 3 Operand 4
RM ModRM:reg (r, w) ModRM:r/m (r) NA NA
RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA
FVM ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA
FV ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) NA

Description

Performs a SIMD subtract of the packed integers of the source operand (second operand) from the packed integers of the destination operand (first operand), and stores the packed integer results in the destination operand. See Figure 9-4 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a SIMD operation. Overflow is handled with wraparound, as described in the following paragraphs.

The (V)PSUBB instruction subtracts packed byte integers. When an individual result is too large or too small to be represented in a byte, the result is wrapped around and the low 8 bits are written to the destination element.

The (V)PSUBW instruction subtracts packed word integers. When an individual result is too large or too small to be represented in a word, the result is wrapped around and the low 16 bits are written to the destination element.

The (V)PSUBD instruction subtracts packed doubleword integers. When an individual result is too large or too small to be represented in a doubleword, the result is wrapped around and the low 32 bits are written to the destination element.

Note that the (V)PSUBB, (V)PSUBW, and (V)PSUBD instructions can operate on either unsigned or signed (two's complement notation) packed integers; however, it does not set bits in the EFLAGS register to indicate overflow and/or a carry. To prevent undetected overflow conditions, software must control the ranges of values upon which it operates.

In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).

Legacy SSE version 64-bit operand: The destination operand must be an MMX technology register and the source operand can be either an MMX technology register or a 64-bit memory location.

128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM desti-nation register remain unchanged.

VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register are zeroed.

VEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory location. The first source operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.

EVEX encoded VPSUBD: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-tion or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with writemask k1.

EVEX encoded VPSUBB/W: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination is condi-tionally updated with writemask k1.

Operation

PSUBB (with 64-bit operands)

    DEST[7:0] ← DEST[7:0] − SRC[7:0];
    (* Repeat subtract operation for 2nd through 7th byte *)
    DEST[63:56] ← DEST[63:56] − SRC[63:56];

PSUBW (with 64-bit operands)

    DEST[15:0] ← DEST[15:0] − SRC[15:0];
    (* Repeat subtract operation for 2nd and 3rd word *)
    DEST[63:48] ← DEST[63:48] − SRC[63:48];

PSUBD (with 64-bit operands)

    DEST[31:0] ← DEST[31:0] − SRC[31:0];
    DEST[63:32] ← DEST[63:32] − SRC[63:32];

PSUBD (with 128-bit operands)

    DEST[31:0]  ← DEST[31:0] − SRC[31:0];
    (* Repeat subtract operation for 2nd and 3rd doubleword *)
    DEST[127:96] ← DEST[127:96] − SRC[127:96];

VPSUBB (EVEX encoded versions)

(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 8
    IF k1[j] OR *no writemask*
         THEN DEST[i+7:i] (cid:197) SRC1[i+7:i] - SRC2[i+7:i]
         ELSE
              IF *merging-masking*
                                                         ; merging-masking
                    THEN *DEST[i+7:i] remains unchanged*
                    ELSE *zeroing-masking*
                                                               ; zeroing-masking
                         DEST[i+7:i] = 0
              FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] (cid:197) 0

VPSUBW (EVEX encoded versions)

(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 16
    IF k1[j] OR *no writemask*
         THEN DEST[i+15:i] (cid:197) SRC1[i+15:i] - SRC2[i+15:i]
         ELSE
              IF *merging-masking*
                                                         ; merging-masking
                    THEN *DEST[i+15:i] remains unchanged*
                    ELSE *zeroing-masking*
                                                              ; zeroing-masking
                         DEST[i+15:i] = 0
              FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] (cid:197) 0

VPSUBD (EVEX encoded versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 32
    IF k1[j] OR *no writemask* THEN
              IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+31:i] (cid:197) SRC1[i+31:i] - SRC2[31:0]
                    ELSE DEST[i+31:i] (cid:197) SRC1[i+31:i] - SRC2[i+31:i]
              FI;
         ELSE
              IF *merging-masking*
                                                         ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*
                                                              ; zeroing-masking
                         DEST[i+31:i] (cid:197) 0
              FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] (cid:197) 0

VPSUBB (VEX.256 encoded version)

DEST[7:0] (cid:197)SRC1[7:0]-SRC2[7:0]
DEST[15:8] (cid:197)SRC1[15:8]-SRC2[15:8]
DEST[23:16] (cid:197)SRC1[23:16]-SRC2[23:16]
DEST[31:24] (cid:197)SRC1[31:24]-SRC2[31:24]
DEST[39:32] (cid:197)SRC1[39:32]-SRC2[39:32]
DEST[47:40] (cid:197)SRC1[47:40]-SRC2[47:40]
DEST[55:48] (cid:197)SRC1[55:48]-SRC2[55:48]
DEST[63:56] (cid:197)SRC1[63:56]-SRC2[63:56]
DEST[71:64] (cid:197)SRC1[71:64]-SRC2[71:64]
DEST[79:72] (cid:197)SRC1[79:72]-SRC2[79:72]
DEST[87:80] (cid:197)SRC1[87:80]-SRC2[87:80]
DEST[95:88] (cid:197)SRC1[95:88]-SRC2[95:88]
DEST[103:96] (cid:197)SRC1[103:96]-SRC2[103:96]
DEST[111:104] (cid:197)SRC1[111:104]-SRC2[111:104]
DEST[119:112] (cid:197)SRC1[119:112]-SRC2[119:112]
DEST[127:120] (cid:197)SRC1[127:120]-SRC2[127:120]
DEST[135:128] (cid:197)SRC1[135:128]-SRC2[135:128]
DEST[143:136] (cid:197)SRC1[143:136]-SRC2[143:136]
DEST[151:144] (cid:197)SRC1[151:144]-SRC2[151:144]
DEST[159:152] (cid:197)SRC1[159:152]-SRC2[159:152]
DEST[167:160] (cid:197)SRC1[167:160]-SRC2[167:160]
DEST[175:168] (cid:197)SRC1[175:168]-SRC2[175:168]
DEST[183:176] (cid:197)SRC1[183:176]-SRC2[183:176]
DEST[191:184] (cid:197)SRC1[191:184]-SRC2[191:184]
DEST[199:192] (cid:197)SRC1[199:192]-SRC2[199:192]
DEST[207:200] (cid:197)SRC1[207:200]-SRC2[207:200]
DEST[215:208] (cid:197)SRC1[215:208]-SRC2[215:208]
DEST[223:216] (cid:197)SRC1[223:216]-SRC2[223:216]
DEST[231:224] (cid:197)SRC1[231:224]-SRC2[231:224]
DEST[239:232] (cid:197)SRC1[239:232]-SRC2[239:232]
DEST[247:240] (cid:197)SRC1[247:240]-SRC2[247:240]
DEST[255:248] (cid:197)SRC1[255:248]-SRC2[255:248]
DEST[MAX_VL-1:256] (cid:197)0

VPSUBB (VEX.128 encoded version)

DEST[7:0] (cid:197)SRC1[7:0]-SRC2[7:0]
DEST[15:8] (cid:197)SRC1[15:8]-SRC2[15:8]
DEST[23:16] (cid:197)SRC1[23:16]-SRC2[23:16]
DEST[31:24] (cid:197)SRC1[31:24]-SRC2[31:24]
DEST[39:32] (cid:197)SRC1[39:32]-SRC2[39:32]
DEST[47:40] (cid:197)SRC1[47:40]-SRC2[47:40]
DEST[55:48] (cid:197)SRC1[55:48]-SRC2[55:48]
DEST[63:56] (cid:197)SRC1[63:56]-SRC2[63:56]
DEST[71:64] (cid:197)SRC1[71:64]-SRC2[71:64]
DEST[79:72] (cid:197)SRC1[79:72]-SRC2[79:72]
DEST[87:80] (cid:197)SRC1[87:80]-SRC2[87:80]
DEST[95:88] (cid:197)SRC1[95:88]-SRC2[95:88]
DEST[103:96] (cid:197)SRC1[103:96]-SRC2[103:96]
DEST[111:104] (cid:197)SRC1[111:104]-SRC2[111:104]
DEST[119:112] (cid:197)SRC1[119:112]-SRC2[119:112]
DEST[127:120] (cid:197)SRC1[127:120]-SRC2[127:120]
DEST[MAX_VL-1:128] (cid:197)0

PSUBB (128-bit Legacy SSE version)

DEST[7:0] (cid:197)DEST[7:0]-SRC[7:0]
DEST[15:8] (cid:197)DEST[15:8]-SRC[15:8]
DEST[23:16] (cid:197)DEST[23:16]-SRC[23:16]
DEST[31:24] (cid:197)DEST[31:24]-SRC[31:24]
DEST[39:32] (cid:197)DEST[39:32]-SRC[39:32]
DEST[47:40] (cid:197)DEST[47:40]-SRC[47:40]
DEST[55:48] (cid:197)DEST[55:48]-SRC[55:48]
DEST[63:56] (cid:197)DEST[63:56]-SRC[63:56]
DEST[71:64] (cid:197)DEST[71:64]-SRC[71:64]
DEST[79:72] (cid:197)DEST[79:72]-SRC[79:72]
DEST[87:80] (cid:197)DEST[87:80]-SRC[87:80]
DEST[95:88] (cid:197)DEST[95:88]-SRC[95:88]
DEST[103:96] (cid:197)DEST[103:96]-SRC[103:96]
DEST[111:104] (cid:197)DEST[111:104]-SRC[111:104]
DEST[119:112] (cid:197)DEST[119:112]-SRC[119:112]
DEST[127:120] (cid:197)DEST[127:120]-SRC[127:120]
DEST[MAX_VL-1:128] (Unmodified)

VPSUBW (VEX.256 encoded version)

DEST[15:0] (cid:197)SRC1[15:0]-SRC2[15:0]
DEST[31:16] (cid:197)SRC1[31:16]-SRC2[31:16]
DEST[47:32] (cid:197)SRC1[47:32]-SRC2[47:32]
DEST[63:48] (cid:197)SRC1[63:48]-SRC2[63:48]
DEST[79:64] (cid:197)SRC1[79:64]-SRC2[79:64]
DEST[95:80] (cid:197)SRC1[95:80]-SRC2[95:80]
DEST[111:96] (cid:197)SRC1[111:96]-SRC2[111:96]
DEST[127:112] (cid:197)SRC1[127:112]-SRC2[127:112]
DEST[143:128] (cid:197)SRC1[143:128]-SRC2[143:128]
DEST[159:144] (cid:197)SRC1[159:144]-SRC2[159:144]
DEST[175:160] (cid:197)SRC1[175:160]-SRC2[175:160]
DEST[191:176] (cid:197)SRC1[191:176]-SRC2[191:176]
DEST[207:192] (cid:197)SRC1207:192]-SRC2[207:192]
DEST[223:208] (cid:197)SRC1[223:208]-SRC2[223:208]
DEST[239:224] (cid:197)SRC1[239:224]-SRC2[239:224]
DEST[255:240] (cid:197)SRC1[255:240]-SRC2[255:240]
DEST[MAX_VL-1:256] (cid:197)0

VPSUBW (VEX.128 encoded version)

DEST[15:0] (cid:197)SRC1[15:0]-SRC2[15:0]
DEST[31:16] (cid:197)SRC1[31:16]-SRC2[31:16]
DEST[47:32] (cid:197)SRC1[47:32]-SRC2[47:32]
DEST[63:48] (cid:197)SRC1[63:48]-SRC2[63:48]
DEST[79:64] (cid:197)SRC1[79:64]-SRC2[79:64]
DEST[95:80] (cid:197)SRC1[95:80]-SRC2[95:80]
DEST[111:96] (cid:197)SRC1[111:96]-SRC2[111:96]
DEST[127:112] (cid:197)SRC1[127:112]-SRC2[127:112]
DEST[MAX_VL-1:128] (cid:197)0

PSUBW (128-bit Legacy SSE version)

DEST[15:0] (cid:197)DEST[15:0]-SRC[15:0]
DEST[31:16] (cid:197)DEST[31:16]-SRC[31:16]
DEST[47:32] (cid:197)DEST[47:32]-SRC[47:32]
DEST[63:48] (cid:197)DEST[63:48]-SRC[63:48]
DEST[79:64] (cid:197)DEST[79:64]-SRC[79:64]
DEST[95:80] (cid:197)DEST[95:80]-SRC[95:80]
DEST[111:96] (cid:197)DEST[111:96]-SRC[111:96]
DEST[127:112] (cid:197)DEST[127:112]-SRC[127:112]
DEST[MAX_VL-1:128] (Unmodified)

VPSUBD (VEX.256 encoded version)

DEST[31:0] (cid:197)SRC1[31:0]-SRC2[31:0]
DEST[63:32] (cid:197)SRC1[63:32]-SRC2[63:32]
DEST[95:64] (cid:197)SRC1[95:64]-SRC2[95:64]
DEST[127:96] (cid:197)SRC1[127:96]-SRC2[127:96]
DEST[159:128] (cid:197)SRC1[159:128]-SRC2[159:128]
DEST[191:160] (cid:197)SRC1[191:160]-SRC2[191:160]
DEST[223:192] (cid:197)SRC1[223:192]-SRC2[223:192]
DEST[255:224] (cid:197)SRC1[255:224]-SRC2[255:224]
DEST[MAX_VL-1:256] (cid:197)0

VPSUBD (VEX.128 encoded version)

DEST[31:0] (cid:197)SRC1[31:0]-SRC2[31:0]
DEST[63:32] (cid:197)SRC1[63:32]-SRC2[63:32]
DEST[95:64] (cid:197)SRC1[95:64]-SRC2[95:64]
DEST[127:96] (cid:197)SRC1[127:96]-SRC2[127:96]
DEST[MAX_VL-1:128] (cid:197)0

PSUBD (128-bit Legacy SSE version)

DEST[31:0] (cid:197)DEST[31:0]-SRC[31:0]
DEST[63:32] (cid:197)DEST[63:32]-SRC[63:32]
DEST[95:64] (cid:197)DEST[95:64]-SRC[95:64]
DEST[127:96] (cid:197)DEST[127:96]-SRC[127:96]
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalents

VPSUBB __m512i _mm512_sub_epi8(__m512i a, __m512i b);

VPSUBB __m512i _mm512_mask_sub_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);

VPSUBB __m512i _mm512_maskz_sub_epi8( __mmask64 k, __m512i a, __m512i b);

VPSUBB __m256i _mm256_mask_sub_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);

VPSUBB __m256i _mm256_maskz_sub_epi8( __mmask32 k, __m256i a, __m256i b);

VPSUBB __m128i _mm_mask_sub_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);

VPSUBB __m128i _mm_maskz_sub_epi8( __mmask16 k, __m128i a, __m128i b);

VPSUBW __m512i _mm512_sub_epi16(__m512i a, __m512i b);

VPSUBW __m512i _mm512_mask_sub_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);

VPSUBW __m512i _mm512_maskz_sub_epi16( __mmask32 k, __m512i a, __m512i b);

VPSUBW __m256i _mm256_mask_sub_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);

VPSUBW __m256i _mm256_maskz_sub_epi16( __mmask16 k, __m256i a, __m256i b);

VPSUBW __m128i _mm_mask_sub_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);

VPSUBW __m128i _mm_maskz_sub_epi16( __mmask8 k, __m128i a, __m128i b);

VPSUBD __m512i _mm512_sub_epi32(__m512i a, __m512i b);

VPSUBD __m512i _mm512_mask_sub_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);

VPSUBD __m512i _mm512_maskz_sub_epi32( __mmask16 k, __m512i a, __m512i b);

VPSUBD __m256i _mm256_mask_sub_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);

VPSUBD __m256i _mm256_maskz_sub_epi32( __mmask8 k, __m256i a, __m256i b);

VPSUBD __m128i _mm_mask_sub_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);

VPSUBD __m128i _mm_maskz_sub_epi32( __mmask8 k, __m128i a, __m128i b);

PSUBB:__m64 _mm_sub_pi8(__m64 m1, __m64 m2)

(V)PSUBB:__m128i _mm_sub_epi8 ( __m128i a, __m128i b)

VPSUBB:__m256i _mm256_sub_epi8 ( __m256i a, __m256i b)

PSUBW:__m64 _mm_sub_pi16(__m64 m1, __m64 m2)

(V)PSUBW:__m128i _mm_sub_epi16 ( __m128i a, __m128i b)

VPSUBW:__m256i _mm256_sub_epi16 ( __m256i a, __m256i b)

PSUBD:__m64 _mm_sub_pi32(__m64 m1, __m64 m2)

(V)PSUBD:__m128i _mm_sub_epi32 ( __m128i a, __m128i b)

VPSUBD:__m256i _mm256_sub_epi32 ( __m256i a, __m256i b)

Flags Affected

None.

Numeric Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Exceptions Type 4.

EVEX-encoded VPSUBD, see Exceptions Type E4.
EVEX-encoded VPSUBB/W, see Exceptions Type E4.nb.