PACKSSWB/PACKSSDW—Pack with Signed Saturation

CPUID Feature Flag	Description	Opcode/Instruction	Op/En	64/32 bit Mode Support
MMX	Converts 4 packed signed word integers from mm1 and from mm2/m64 into 8 packed signed byte integers in mm1 using signed saturation.	0F 63 /r¹ PACKSSWB mm1, mm2/m64	RM	V/V
SSE2	Converts 8 packed signed word integers from xmm1 and from xxm2/m128 into 16 packed signed byte integers in xxm1 using signed saturation.	66 0F 63 /r PACKSSWB xmm1, xmm2/m128	RM	V/V
MMX	Converts 2 packed signed doubleword integers from mm1 and from mm2/m64 into 4 packed signed word integers in mm1 using signed saturation.	0F 6B /r¹ PACKSSDW mm1, mm2/m64	RM	V/V
SSE2	Converts 4 packed signed doubleword integers from xmm1 and from xxm2/m128 into 8 packed signed word integers in xxm1 using signed saturation.	66 0F 6B /r PACKSSDW xmm1, xmm2/m128	RM	V/V
AVX	Converts 8 packed signed word integers from xmm2 and from xmm3/m128 into 16 packed signed byte integers in xmm1 using signed saturation.	VEX.NDS.128.66.0F.WIG 63 /r VPACKSSWB xmm1,xmm2, xmm3/m128	RVM	V/V
AVX	Converts 4 packed signed doubleword integers from xmm2 and from xmm3/m128 into 8 packed signed word integers in xmm1 using signed saturation.	VEX.NDS.128.66.0F.WIG 6B /r VPACKSSDW xmm1,xmm2, xmm3/m128	RVM	V/V
AVX2	Converts 16 packed signed word integers from ymm2 and from ymm3/m256 into 32 packed signed byte integers in ymm1 using signed saturation.	VEX.NDS.256.66.0F.WIG 63 /r VPACKSSWB ymm1, ymm2, ymm3/m256	RVM	V/V
AVX2	Converts 8 packed signed doubleword integers from ymm2 and from ymm3/m256 into 16 packed signed word integers in ymm1using signed saturation.	VEX.NDS.256.66.0F.WIG 6B /r VPACKSSDW ymm1, ymm2, ymm3/m256	RVM	V/V
AVX512VL AVX512BW	Converts packed signed word integers from xmm2 and from xmm3/m128 into packed signed byte integers in xmm1 using signed saturation under writemask k1.	EVEX.NDS.128.66.0F.WIG 63 /r VPACKSSWB xmm1 {k1}{z}, xmm2, xmm3/m128	FVM	V/V
AVX512VL AVX512BW	Converts packed signed word integers from ymm2 and from ymm3/m256 into packed signed byte integers in ymm1 using signed saturation under writemask k1.	EVEX.NDS.256.66.0F.WIG 63 /r VPACKSSWB ymm1 {k1}{z}, ymm2, ymm3/m256	FVM	V/V
AVX512BW	Converts packed signed word integers from zmm2 and from zmm3/m512 into packed signed byte integers in zmm1 using signed saturation under writemask k1.	EVEX.NDS.512.66.0F.WIG 63 /r VPACKSSWB zmm1 {k1}{z}, zmm2, zmm3/m512	FVM	V/V
AVX512VL AVX512BW	Converts packed signed doubleword integers from xmm2 and from xmm3/m128/m32bcst into packed signed word integers in xmm1 using signed saturation under writemask k1.	EVEX.NDS.128.66.0F.W0 6B /r VPACKSSDW xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst	FV	V/V

EVEX.NDS.256.66.0F.W0 6B /r

VPACKSSDW ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst

V/V

AVX512VL

AVX512BW

Converts packed signed doubleword integers from ymm2 and from ymm3/m256/m32bcst into packed signed word integers in ymm1 using signed saturation under writemask k1.

EVEX.NDS.512.66.0F.W0 6B /r

VPACKSSDW zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst

V/V

AVX512BW

Converts packed signed doubleword integers from zmm2 and from zmm3/m512/m32bcst into packed signed word integers in zmm1 using signed saturation under writemask k1.

NOTES:

1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En	Operand 1	Operand 2	Operand 3	Operand 4
RM	ModRM:reg (r, w)	ModRM:r/m (r)	NA	NA
RVM	ModRM:reg (w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
FVM	ModRM:reg (w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA
FV	ModRM:reg (w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

Description

Converts packed signed word integers into packed signed byte integers (PACKSSWB) or converts packed signed doubleword integers into packed signed word integers (PACKSSDW), using saturation to handle overflow condi-tions. See Figure 4-6 for an example of the packing operation.

Figure 4-6. Operation of the PACKSSDW Instruction Using 64-bit Operands

PACKSSWB converts packed signed word integers in the first and second source operands into packed signed byte integers using signed saturation to handle overflow conditions beyond the range of signed byte integers. If the signed doubleword value is beyond the range of an unsigned word (i.e. greater than 7FH or less than 80H), the saturated signed byte integer value of 7FH or 80H, respectively, is stored in the destination. PACKSSDW converts packed signed doubleword integers in the first and second source operands into packed signed word integers using signed saturation to handle overflow conditions beyond 7FFFH and 8000H.

EVEX encoded PACKSSWB: The first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM register, updated conditional under the writemask k1.

EVEX encoded PACKSSDW: The first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register, updated conditional under the writemask k1.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are zeroed.

VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are zeroed.

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding ZMM destination register destination are unmodified.

Operation

PACKSSWB instruction (128-bit Legacy SSE version)

DEST[7:0] (cid:197) SaturateSignedWordToSignedByte (DEST[15:0]);

DEST[15:8] (cid:197) SaturateSignedWordToSignedByte (DEST[31:16]);

DEST[23:16] (cid:197) SaturateSignedWordToSignedByte (DEST[47:32]);

DEST[31:24] (cid:197) SaturateSignedWordToSignedByte (DEST[63:48]);

DEST[39:32] (cid:197) SaturateSignedWordToSignedByte (DEST[79:64]);

DEST[47:40] (cid:197) SaturateSignedWordToSignedByte (DEST[95:80]);

DEST[55:48] (cid:197) SaturateSignedWordToSignedByte (DEST[111:96]);

DEST[63:56] (cid:197) SaturateSignedWordToSignedByte (DEST[127:112]);

DEST[71:64] (cid:197) SaturateSignedWordToSignedByte (SRC[15:0]);

DEST[79:72] (cid:197) SaturateSignedWordToSignedByte (SRC[31:16]);

DEST[87:80] (cid:197) SaturateSignedWordToSignedByte (SRC[47:32]);

DEST[95:88] (cid:197) SaturateSignedWordToSignedByte (SRC[63:48]);

DEST[103:96] (cid:197) SaturateSignedWordToSignedByte (SRC[79:64]);

DEST[111:104] (cid:197) SaturateSignedWordToSignedByte (SRC[95:80]);

DEST[119:112] (cid:197) SaturateSignedWordToSignedByte (SRC[111:96]);

DEST[127:120] (cid:197) SaturateSignedWordToSignedByte (SRC[127:112]);

DEST[MAX_VL-1:128] (Unmodified)

PACKSSDW instruction (128-bit Legacy SSE version)

DEST[15:0] (cid:197) SaturateSignedDwordToSignedWord (DEST[31:0]);

DEST[31:16] (cid:197) SaturateSignedDwordToSignedWord (DEST[63:32]);

DEST[47:32] (cid:197) SaturateSignedDwordToSignedWord (DEST[95:64]);

DEST[63:48] (cid:197) SaturateSignedDwordToSignedWord (DEST[127:96]);

DEST[79:64] (cid:197) SaturateSignedDwordToSignedWord (SRC[31:0]);

DEST[95:80] (cid:197) SaturateSignedDwordToSignedWord (SRC[63:32]);

DEST[111:96] (cid:197) SaturateSignedDwordToSignedWord (SRC[95:64]);

DEST[127:112] (cid:197) SaturateSignedDwordToSignedWord (SRC[127:96]);

DEST[MAX_VL-1:128] (Unmodified)

VPACKSSWB instruction (VEX.128 encoded version)

DEST[7:0] (cid:197) SaturateSignedWordToSignedByte (SRC1[15:0]);

DEST[15:8] (cid:197) SaturateSignedWordToSignedByte (SRC1[31:16]);

DEST[23:16] (cid:197) SaturateSignedWordToSignedByte (SRC1[47:32]);

DEST[31:24] (cid:197) SaturateSignedWordToSignedByte (SRC1[63:48]);

DEST[39:32] (cid:197) SaturateSignedWordToSignedByte (SRC1[79:64]);

DEST[47:40] (cid:197) SaturateSignedWordToSignedByte (SRC1[95:80]);

DEST[55:48] (cid:197) SaturateSignedWordToSignedByte (SRC1[111:96]);

DEST[63:56] (cid:197) SaturateSignedWordToSignedByte (SRC1[127:112]);

DEST[71:64] (cid:197) SaturateSignedWordToSignedByte (SRC2[15:0]);

DEST[79:72] (cid:197) SaturateSignedWordToSignedByte (SRC2[31:16]);

DEST[87:80] (cid:197) SaturateSignedWordToSignedByte (SRC2[47:32]);

DEST[95:88] (cid:197) SaturateSignedWordToSignedByte (SRC2[63:48]);

DEST[103:96] (cid:197) SaturateSignedWordToSignedByte (SRC2[79:64]);

DEST[111:104] (cid:197) SaturateSignedWordToSignedByte (SRC2[95:80]);

DEST[119:112] (cid:197) SaturateSignedWordToSignedByte (SRC2[111:96]);

DEST[127:120] (cid:197) SaturateSignedWordToSignedByte (SRC2[127:112]);

DEST[MAX_VL-1:128] (cid:197) 0;

VPACKSSDW instruction (VEX.128 encoded version)

DEST[15:0] (cid:197) SaturateSignedDwordToSignedWord (SRC1[31:0]);

DEST[31:16] (cid:197) SaturateSignedDwordToSignedWord (SRC1[63:32]);

DEST[47:32] (cid:197) SaturateSignedDwordToSignedWord (SRC1[95:64]);

DEST[63:48] (cid:197) SaturateSignedDwordToSignedWord (SRC1[127:96]);

DEST[79:64] (cid:197) SaturateSignedDwordToSignedWord (SRC2[31:0]);

DEST[95:80] (cid:197) SaturateSignedDwordToSignedWord (SRC2[63:32]);

DEST[111:96] (cid:197) SaturateSignedDwordToSignedWord (SRC2[95:64]);

DEST[127:112] (cid:197) SaturateSignedDwordToSignedWord (SRC2[127:96]);

DEST[MAX_VL-1:128] (cid:197) 0;

VPACKSSWB instruction (VEX.256 encoded version)