MOVDQA,VMOVDQA32/64—Move Aligned Packed Integer Values

Instruction Operand Encoding

Description

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

EVEX encoded versions:

Moves 128, 256 or 512 bits of packed doubleword/quadword integer values from the source operand (the second operand) to the destination operand (the first operand). This instruction can be used to load a vector register from an int32/int64 memory location, to store the contents of a vector register into an int32/int64 memory location, or to move data between two ZMM registers. When the source or destination operand is a memory operand, the operand must be aligned on a 16 (EVEX.128)/32(EVEX.256)/64(EVEX.512)-byte boundary or a general-protection exception (#GP) will be generated. To move integer data to and from unaligned memory locations, use the VMOVDQU instruction.

The destination operand is updated at 32-bit (VMOVDQA32) or 64-bit (VMOVDQA64) granularity according to the writemask.

VEX.256 encoded version:

Moves 256 bits of packed integer values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory location, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM registers.

When the source or destination operand is a memory operand, the operand must be aligned on a 32-byte boundary or a general-protection exception (#GP) will be generated. To move integer data to and from unaligned memory locations, use the VMOVDQU instruction. Bits (MAX_VL-1:256) of the destination register are zeroed.

128-bit versions:

Moves 128 bits of packed integer values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory location, to store the contents of an XMM register into a 128-bit memory location, or to move data between two XMM registers.

When the source or destination operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated. To move integer data to and from unaligned memory locations, use the VMOVDQU instruction.

128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding ZMM destination register remain unchanged.

VEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed.

Operation

VMOVDQA32 (EVEX encoded versions, register-copy form)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j (cid:197) 0 TO KL-1

i (cid:197) j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] (cid:197) SRC[i+31:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE DEST[i+31:i] (cid:197) 0

; zeroing-masking

FI

FI;

ENDFOR

DEST[MAX_VL-1:VL] (cid:197) 0

VMOVDQA32 (EVEX encoded versions, store-form)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j (cid:197) 0 TO KL-1

i (cid:197) j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i](cid:197) SRC[i+31:i]

ELSE *DEST[i+31:i] remains unchanged*

; merging-masking

FI;

ENDFOR;

VMOVDQA32 (EVEX encoded versions, load-form)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j (cid:197) 0 TO KL-1

i (cid:197) j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i] (cid:197) SRC[i+31:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE DEST[i+31:i] (cid:197) 0

; zeroing-masking

FI

FI;

ENDFOR

DEST[MAX_VL-1:VL] (cid:197) 0

VMOVDQA64 (EVEX encoded versions, register-copy form)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j (cid:197) 0 TO KL-1

i (cid:197) j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] (cid:197) SRC[i+63:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE DEST[i+63:i] (cid:197) 0

; zeroing-masking

FI

FI;

ENDFOR

DEST[MAX_VL-1:VL] (cid:197) 0

VMOVDQA64 (EVEX encoded versions, store-form)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j (cid:197) 0 TO KL-1

i (cid:197) j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i](cid:197) SRC[i+63:i]

ELSE *DEST[i+63:i] remains unchanged*

; merging-masking

FI;

ENDFOR;

VMOVDQA64 (EVEX encoded versions, load-form)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j (cid:197) 0 TO KL-1

i (cid:197) j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i] (cid:197) SRC[i+63:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE DEST[i+63:i] (cid:197) 0

; zeroing-masking

FI

FI;

ENDFOR

DEST[MAX_VL-1:VL] (cid:197) 0

VMOVDQA (VEX.256 encoded version, load - and register copy)

DEST[255:0] (cid:197) SRC[255:0]

DEST[MAX_VL-1:256] (cid:197) 0

VMOVDQA (VEX.256 encoded version, store-form)

DEST[255:0] (cid:197) SRC[255:0] VMOVDQA (VEX.128 encoded version)

DEST[127:0] (cid:197) SRC[127:0]

DEST[MAX_VL-1:128] (cid:197) 0

VMOVDQA (128-bit load- and register-copy- form Legacy SSE version)

DEST[127:0] (cid:197) SRC[127:0]

DEST[MAX_VL-1:128] (Unmodified)

(V)MOVDQA (128-bit store-form version)

DEST[127:0] (cid:197) SRC[127:0]

Intel C/C++ Compiler Intrinsic Equivalent

VMOVDQA32 __m512i _mm512_load_epi32( void * sa);

VMOVDQA32 __m512i _mm512_mask_load_epi32(__m512i s, __mmask16 k, void * sa);

VMOVDQA32 __m512i _mm512_maskz_load_epi32( __mmask16 k, void * sa);

VMOVDQA32 void _mm512_store_epi32(void * d, __m512i a);

VMOVDQA32 void _mm512_mask_store_epi32(void * d, __mmask16 k, __m512i a);

VMOVDQA32 __m256i _mm256_mask_load_epi32(__m256i s, __mmask8 k, void * sa);

VMOVDQA32 __m256i _mm256_maskz_load_epi32( __mmask8 k, void * sa);

VMOVDQA32 void _mm256_store_epi32(void * d, __m256i a);

VMOVDQA32 void _mm256_mask_store_epi32(void * d, __mmask8 k, __m256i a);

VMOVDQA32 __m128i _mm_mask_load_epi32(__m128i s, __mmask8 k, void * sa);

VMOVDQA32 __m128i _mm_maskz_load_epi32( __mmask8 k, void * sa);

VMOVDQA32 void _mm_store_epi32(void * d, __m128i a);

VMOVDQA32 void _mm_mask_store_epi32(void * d, __mmask8 k, __m128i a);

VMOVDQA64 __m512i _mm512_load_epi64( void * sa);

VMOVDQA64 __m512i _mm512_mask_load_epi64(__m512i s, __mmask8 k, void * sa);

VMOVDQA64 __m512i _mm512_maskz_load_epi64( __mmask8 k, void * sa);

VMOVDQA64 void _mm512_store_epi64(void * d, __m512i a);

VMOVDQA64 void _mm512_mask_store_epi64(void * d, __mmask8 k, __m512i a);

VMOVDQA64 __m256i _mm256_mask_load_epi64(__m256i s, __mmask8 k, void * sa);

VMOVDQA64 __m256i _mm256_maskz_load_epi64( __mmask8 k, void * sa);

VMOVDQA64 void _mm256_store_epi64(void * d, __m256i a);

VMOVDQA64 void _mm256_mask_store_epi64(void * d, __mmask8 k, __m256i a);

VMOVDQA64 __m128i _mm_mask_load_epi64(__m128i s, __mmask8 k, void * sa);

VMOVDQA64 __m128i _mm_maskz_load_epi64( __mmask8 k, void * sa);

VMOVDQA64 void _mm_store_epi64(void * d, __m128i a);

VMOVDQA64 void _mm_mask_store_epi64(void * d, __mmask8 k, __m128i a);

MOVDQA void __m256i _mm256_load_si256 (__m256i * p);

MOVDQA _mm256_store_si256(_m256i *p, __m256i a);

MOVDQA __m128i _mm_load_si128 (__m128i * p);

MOVDQA void _mm_store_si128(__m128i *p, __m128i a);

SIMD Floating-Point Exceptions

None

Other Exceptions

Non-EVEX-encoded instruction, see Exceptions Type1.SSE2;