| Opcode/Instruction | Op /En | 64/32 bit Mode Support | CPUID Feature Flag | Description |
|---|---|---|---|---|
| 0F 58 /r ADDPS xmm1, xmm2/m128 | RM | V/V | SSE | Add packed single-precision floating-point values from xmm2/m128 to xmm1 and store result in xmm1. |
| VEX.NDS.128.0F.WIG 58 /r VADDPS xmm1,xmm2, xmm3/m128 | RVM | V/V | AVX | Add packed single-precision floating-point values from xmm3/m128 to xmm2 and store result in xmm1. |
| VEX.NDS.256.0F.WIG 58 /r VADDPS ymm1, ymm2, ymm3/m256 | RVM | V/V | AVX | Add packed single-precision floating-point values from ymm3/m256 to ymm2 and store result in ymm1. |
| EVEX.NDS.128.0F.W0 58 /r VADDPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst | FV | V/V | AVX512VL AVX512F | Add packed single-precision floating-point values from xmm3/m128/m32bcst to xmm2 and store result in xmm1 with writemask k1. |
| EVEX.NDS.256.0F.W0 58 /r VADDPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst | FV | V/V | AVX512VL AVX512F | Add packed single-precision floating-point values from ymm3/m256/m32bcst to ymm2 and store result in ymm1 with writemask k1. |
| EVEX.NDS.512.0F.W0 58 /r VADDPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst {er} | FV | V/V | AVX512F | Add packed single-precision floating-point values from zmm3/m512/m32bcst to zmm2 and store result in zmm1 with writemask k1. |
| Op/En | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
| RM | ModRM:reg (r, w) | ModRM:r/m (r) | NA | NA |
| RVM | ModRM:reg (w) | VEX.vvvv | ModRM:r/m (r) | NA |
| FV-RVM | ModRM:reg (w) | EVEX.vvvv | ModRM:r/m (r) | NA |
Add four, eight or sixteen packed single-precision floating-point values from the first source operand with the second source operand, and stores the packed single-precision floating-point results in the destination operand.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are zeroed.
VEX.128 encoded version: the first source operand is a XMM register. The second source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-nation is not distinct from the first source XMM register and the upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.
VADDPS (EVEX encoded versions) when src2 operand is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j (cid:197) 0 TO KL-1
i (cid:197) j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] (cid:197) SRC1[i+31:i] + SRC2[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] (cid:197) 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] (cid:197) 0
VADDPS (EVEX encoded versions) when src2 operand is a memory source
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j (cid:197) 0 TO KL-1
i (cid:197)j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i] (cid:197) SRC1[i+31:i] + SRC2[31:0]
ELSE
DEST[i+31:i] (cid:197) SRC1[i+31:i] + SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] (cid:197) 0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL] (cid:197) 0
VADDPS (VEX.256 encoded version)
DEST[31:0] (cid:197) SRC1[31:0] + SRC2[31:0] DEST[63:32] (cid:197) SRC1[63:32] + SRC2[63:32] DEST[95:64] (cid:197) SRC1[95:64] + SRC2[95:64] DEST[127:96] (cid:197) SRC1[127:96] + SRC2[127:96] DEST[159:128] (cid:197) SRC1[159:128] + SRC2[159:128] DEST[191:160](cid:197) SRC1[191:160] + SRC2[191:160] DEST[223:192] (cid:197) SRC1[223:192] + SRC2[223:192] DEST[255:224] (cid:197) SRC1[255:224] + SRC2[255:224]. DEST[MAX_VL-1:256] (cid:197) 0
VADDPS (VEX.128 encoded version)
DEST[31:0] (cid:197) SRC1[31:0] + SRC2[31:0] DEST[63:32] (cid:197) SRC1[63:32] + SRC2[63:32] DEST[95:64] (cid:197) SRC1[95:64] + SRC2[95:64] DEST[127:96] (cid:197) SRC1[127:96] + SRC2[127:96] DEST[MAX_VL-1:128] (cid:197) 0 ADDPS (128-bit Legacy SSE version) DEST[31:0] (cid:197) SRC1[31:0] + SRC2[31:0] DEST[63:32] (cid:197) SRC1[63:32] + SRC2[63:32] DEST[95:64] (cid:197) SRC1[95:64] + SRC2[95:64] DEST[127:96] (cid:197) SRC1[127:96] + SRC2[127:96] DEST[MAX_VL-1:128] (Unmodified)
VADDPS __m512 _mm512_add_ps (__m512 a, __m512 b);
VADDPS __m512 _mm512_mask_add_ps (__m512 s, __mmask16 k, __m512 a, __m512 b);
VADDPS __m512 _mm512_maskz_add_ps (__mmask16 k, __m512 a, __m512 b);
VADDPS __m256 _mm256_mask_add_ps (__m256 s, __mmask8 k, __m256 a, __m256 b);
VADDPS __m256 _mm256_maskz_add_ps (__mmask8 k, __m256 a, __m256 b);
VADDPS __m128 _mm_mask_add_ps (__m128d s, __mmask8 k, __m128 a, __m128 b);
VADDPS __m128 _mm_maskz_add_ps (__mmask8 k, __m128 a, __m128 b);
VADDPS __m512 _mm512_add_round_ps (__m512 a, __m512 b, int);
VADDPS __m512 _mm512_mask_add_round_ps (__m512 s, __mmask16 k, __m512 a, __m512 b, int);
VADDPS __m512 _mm512_maskz_add_round_ps (__mmask16 k, __m512 a, __m512 b, int);
ADDPS __m256 _mm256_add_ps (__m256 a, __m256 b);
ADDPS __m128 _mm_add_ps (__m128 a, __m128 b);
Overflow, Underflow, Invalid, Precision, Denormal
| VEX-encoded instruction, see Exceptions Type 2. |
| EVEX-encoded instruction, see Exceptions Type E2. |